The present invention pertains to differential amplifiers. More particularly, the present invention pertains to an improved output circuit stage for a differential amplifier.
Differential amplifiers are used to amplify differential inputs, usually small signal differentials, at any given common mode of operation. Superior performance can be achieved by the differential amplifier which exhibits higher amplification that remains consistent, constant, across a wide common mode range. Typical differential amplifiers are specified as having a Common Mode input Range (CMR) in which a given differential gain is available. Also, typical differential amplifiers are specified with a Common Mode Rejection Ratio (CMRR) which denotes the inconsistent behavior of traditional differential amplifiers at different common modes. The CMRR typically represents a differential gain (as a function of common mode) divided by the common mode gain (which varies at different common modes). To compensate for the deficiencies of limited CMR and inconsistent CMRR across the CMR, many differential amplifiers in analog and mixed-mode chips require higher voltages and inefficient increases in power to meet an adequate range of common modes for acceptable behavior. Despite an immense amount of previous efforts, traditional designs have been notoriously far from ideal, always hampered by the paradoxical bias current inherent in differential pair configurations.
Conventional differential amplifiers use a bias current through a differential transistor pair. In metal oxide semiconductor (MOS) circuits, the differential pair features matched devices with resistive loading at their drains. Increased bias current yields greater differential gain as well as greater common mode gain. Thus, changing the bias current is not a solution to the problem of optimizing the CMRR. This inefficient use of power can be intuitively noted by observing that the lower the bias current the better the differential pair operates, keeping the differential pair transistors in their saturation region and keeping their common source far from a virtual ground that would negate the differential pair configuration. Yet the higher the voltage at their common source, due to the lower bias current, the less the differential gain available from the differential pair. The CMR is constrained by the fact that as the common modes approach the voltage at the common source of the differential pair both transistors in the differential pair will enter into their cutoff region and cease to operate. This is perhaps the most serious limitation of traditional designs, which typically use differential pair configurations.
Prior differential amplifiers also have a few other limitations. Coupling a differential amplifier to a high gain stage, for instance, typically requires level shifting, thus limiting the high gain of that stage. Also the slew rate (SR) is adversely dependent upon the CMRR. That is, when the bias current is kept low for a high CMRR, the SR is decreased.
In view of the above, there is a need for an improved differential amplifier circuit.